When designing a digital circuit, a fundamental goal is to satisfy overall timing constraints. An important part of achieving this goal is controlling the circuit's clock skew, which is the difference between the arrival times of the clock signal at different flip-flops in the circuit. The clock skew may be caused by several things, such as variations in the gate delays of the clock drivers, variations in the loads of the clock drivers, variations in the wire lengths between clock drivers, the position of the memory elements being driven, or the clocking strategy, for example.
The clock skew between two flip-flops in the circuit, FF1 and FF2, should be greater than the hold time minus the shortest path delay. The clock skew should also be smaller than the clock period minus the longest path plus the setup time. Any timing values that respect these constraints will be considered valid.
Traditionally, design methodologies try to meet these timing constraints between flip-flops in a circuit by causing the clock skew to be zero. However, due to deep submicron problems, such as interconnect delay, coupling noise, IR drop, electro-migration, process variation, and on-chip inductance, for example, designing a circuit that operates with a clock skew of zero is very difficult. As a result designers use skew to meet timing constraints.
Historically, two different approaches have been used to take advantage of skew in the circuit, a linear programming approach and a graph based approach. However, both of these approaches require intensive computations, and they also have a high impact on the clock tree.